1. Field of the Invention
The present invention relates to a data output driver, and more particularly, to a data output driver and a semiconductor memory device having the same which can adjust driving capability.
2. Description of the Related Art
A conventional data output driver includes a pull-up driver composed of a predetermined number of pull-up circuits and a pull-down driver composed of a predetermined number of pull-down circuits, and generates output data. Driving capability can be controlled by adjusting the number of enabled pull-up circuits and the number of enabled pull-down circuits constituting the pull-up driver and the pull-down driver, respectively, and the slopes of rising and falling transition of the output data can be adjusted by differing operating times of the pull-up circuits and the pull-down circuits when the output data is transferred.
FIG. 1 illustrates an example of the conventional data output driver, which includes inverters 11 and 12, a pull-up driver 10, a pull-down driver 20, a rising transition slope adjuster 30, a falling transition slope adjuster 40, a pull-up drive control signal generator 50, and a pull-down drive control signal generator 60.
Referring to FIG. 1, the pull-up driver 10 consists of n pull-up circuits 10-1 to 10-n, the pull-down driver 20 consists of n pull-down circuits 20-1 to 20-n, each of the n pull-up circuits 10-1 to 10-n consists of a pre driver 12-1 to 12-n and a main driver 14-1 to 14-n, and each of the n pull-down circuits 20-1 to 20-n consists of a pre driver 22-1 to 22-n and a main driver 24-1 to 24-n. Each of the pre drivers 12-1 to 12-n consists of PMOS transistors P1 and P2 and NMOS transistors N1 and N2, each of the main drivers 14-1 to 14-n consists of a PMOS transistor P3, each of the pre drivers 22-1 to 22-n consists of PMOS transistors P4 and P5 and NMOS transistors N3 and N4, and each of the main drivers 24-1 to 24-n consists of an NMOS transistor N5. The rising transition slope adjuster 30 consists of n delay units 30-1 to 30-n connected in a cascade arrangement, and the falling transition slope adjuster 40 consists of n delay units 40-1 to 40-n connected in a cascade arrangement.
Referring to FIG. 1, a control signal CON1 consists of i-bit data to set delay times of the delay units 30-1 to 30-n, and a control signal CON2 consists of i-bit data to set delay times of the delay units 40-1 to 40-n. A control signal CON3 consists of n-bit control signals CON31 to CON3n to enable operation of each of the pull-up circuits 10-1 to 10-n, and a control signal CON4 consists of n-bit control signals CON41 to CON4n to enable operation of each of the pull-down circuits 20-1 to 20-n. 
Operation of the circuits shown in FIG. 1 is now described as follows. First, operation of each of the pull-up circuits 10-1 to 10-n will be described.
When a corresponding bit of the control signal CON3 is at a “low” level, the NMOS transistor N2 is turned off and the PMOS transistor P2 is turned on. Accordingly, a signal of “high” level is applied to a gate of the PMOS transistor P3, which turns the PMOS transistor P3 off. Consequently, the corresponding pull-up circuit is disabled. On the other hand, when the corresponding bit of the control signal CON3 is at a “high” level, the NMOS transistor N2 is turned on and the PMOS transistor P2 is turned off. In this state, a signal of “low” level is applied to a gate of the PMOS transistor P3 when the signal of “high” level is applied to gates of the NMOS transistor N1 and the PMOS transistor P1, and a signal of “high” level is applied to the gate of the PMOS transistor P3 when the signal of “low” level is applied to the gates of the NMOS transistor N1 and the PMOS transistor P1. The PMOS transistor P3 generates output data DQ at a “high” level when the signal of “low” level is applied to its gate.
Delay times of the delay units 30-1 to 30-n of the rising transition slope adjuster 30 are adjusted in response to the control signal CON1, and the pull-up circuits enabled in response to the control signal CON3 among the pull-up circuits 10-1 to 10-n sequentially perform operations in response to the output signal of the inverter I1 delayed by the delay units 30-1 to 30-n. Accordingly, the rising transition slope of the output data DQ is adjusted.
The pull-up drive control signal generator 50 is initially set to a predetermined value, enabled in response to a pull-up control signal PUCON, increases the set value in response to a pull-up increase control signal UICON, and decreases the set value in response to a pull-up decrease control signal UDCON, thereby generating a control signal CON3.
Operation of each of the pull-down circuits 20-1 to 20-n will now be described as follows.
When the corresponding bit of the control signal CON4 is at a “high” level, the PMOS transistor P4 is turned off and the NMOS transistor N4 is turned on so that a signal of “low” level is applied to a gate of the NMOS transistor N5, which turns the NMOS transistor N5 off. Consequently, the corresponding pull-down circuit is disabled. On the other hand, when the corresponding bit of the control signal CON4 is at a “low” level, the PMOS transistor P4 is turned on and the NMOS transistor N4 is turned off. In this state, a signal of “low” level is applied to the gate of the NMOS transistor N5 when the signal of “high” level is applied to the gates of the NMOS transistor N3 and the PMOS transistor P5, and a signal of “high” level is applied to the gate of the NMOS transistor N5 when the signal of “low” level is applied to the gate of the NMOS transistor N5. The NMOS transistor N5 generates output data DQ at a “low” level when the signal of “high” level is applied to its gate.
In the falling transition slope adjuster 40, delay times of the delay units 40-1 to 40-n are adjusted in response to the control signal CON2, and the pull-down circuits enabled in response to the control signal CON4 among the pull-down circuits 20-1 to 20-n sequentially perform operations in response to the output signals of the inverter I2 delayed by the delay units 40-1 to 40-n. Accordingly, the falling transition slope of the output data DQ is adjusted.
The pull-down drive control signal generator 60 is initially set to a predetermined value, enabled in response to a pull-down control signal PDCON, increases the set value in response to a pull-down increase control signal DICON, and decreases the set value in response to a pull-down decrease control signal DDCON, thereby generating the control signal CON4.
The conventional data output driver shown in FIG. 1 could adjust the driving capability of the pull-up and pull-down drivers 10 and 20 in response to the control signals CON3 and CON4, and could adjust the rising and falling transition slopes of the output data DQ in response to the control signals CON1 and CON2.
In general, the delay times of the delay units 30-1 to 30-n and 40-1 to 40-n can be fixed or varied in response to the control signals CON1 and CON2 so that the rising and falling transition slopes of the output data DQ can be adjusted, and the control signals CON3 and CON4 are varied so that the driving capability of the pull-up and pull-down drivers 10 and 20 can be varied.
However, when the driving capability of the data output driver is varied, the rising and falling transition slopes of the output data are also changed. Accordingly, the rising and falling transition slopes may be out of a desired range in response to a change in driving capability. For example, the rising and falling transition slopes increase when the driving capability of the pull-up and pull-down drivers 10 and 20 increase, and decrease when the driving capability decreases. Thus, it is cumbersome to adjust the slope to be within the desired range by varying the delay times of the delay units 30-1 to 30-n and 40-1 to 40-n using the control signals CON1 and CON2. When the delay times of the delay units 30-1 to 30-n and 40-1 to 40-n are fixed in response to the control signals CON1 and CON2, it becomes impossible to adjust the slopes to be within the desired range.
Consequently, it is cumbersome to adjust the slopes again when the rising and falling transition slopes of the output data change in response to a change in driving capability in the conventional data output driver. In some cases, the slopes may not be adjusted at all so that the desired output data cannot be produced.